The present invention generally relates to digital communication terminal equipment, and more particularly to a digital communication terminal equipment which has a bit comparison management system.
A bit comparison management system detects a bit error in a transmission signal caused by a device failure in a digital communication terminal equipment. The device failure may be generated by an operation failure, a circuit failure, a damage to parts or the like.
A description will be given of a conventional bit error detection method, by referring to FIG. 1. For example, a signal from a low-speed group transmission path I is transmitted to a high-speed group transmission path II via a multiplexer or a demultiplexer of a supervised part 10. A reference part 20 converts a high-speed group output signal of the supervised part 10 to a low-speed group signal. A bit comparison supervision part 30 comprises a phase synchronizing part 31, a bit error detecting part 32 and a control part 33.
The phase synchronizing part 31 synchronizes the phase of data patterns of the low-speed group signal which is received from the low-speed group transmission path I and the low-speed group signal which is output from the reference part 20. The bit error detecting part 32 compares corresponding bits of the two synchronized data patterns received from the phase synchronizing part 31 for each bit of the data pattern. When an error is generated in the transmission signal due to a device failure, the corresponding bits of the two data patterns do not match in the bit error detecting part 32 and one bit error is detected for every corresponding bit which does not match. The control part 33 detects a bit comparison error when the number of bit errors detected in the bit error detecting part 32 exceeds a predetermined value within a predetermined time. An alarm signal is output from the control part 33 as a supervision result when the bit comparison error is detected, and this alarm signal is used to switch a connection of the supervised part 10 and the like.
When the device failure occurs, a line switching is made between current-auxiliary systems for the circuit parts and the lines of the digital transmission terminal equipment. This line switching is made based on the above described supervision result which is output from the bit comparison supervision part 30, and for this reason, a high reliability is required of the supervision result.
FIG. 2 shows a conventional digital transmission terminal equipment which is provided with current-auxiliary systems. The digital transmission terminal equipment is provided between low-speed group transmission paths I and IV and high-speed group transmission paths II and III. One of the low-speed group transmission paths I and IV is selected by a switch 6, and one of the high-speed group transmission paths II and III is selected by a switch 7. A low-speed group signal A from the low-speed group transmission path I is supplied to a current multiplexer 1 via the switch 6, and a high-speed group signal B output from the current multiplexer 1 is supplied to the high-speed group transmission path II via the switch 7. The switches 6 and 7 are also used to select one of the current multiplexer 1 and an auxiliary multiplexer 3, and in this case, the switching of the multiplexers 1 and 3 is controlled by a switching control signal SCS which is output from a control part 53 of a bit comparison supervision circuit 5. For example, the low-speed group transmission paths I and IV may respectively have n channels.
The bit comparison supervision circuit 5 includes a phase synchronizing part 51, a bit error detector part 52, the control part 53, a test pattern generator part 54, and a selector part 55.
A current demultiplexer 2 and an auxiliary demultiplexer 4 are provided between the high-speed group transmission path III and the low-speed group transmission path IV via the switches 6 and 7. The demultiplexers 2 and 4 are used to convert the high-speed group signal B into the low-speed group signal A.
The multiplexers 1 and 3 and the demultiplexers 2 and 4 constitute a supervised part, and the auxiliary demultiplexer 4 functions as a reference part for the supervised part. For example, the low-speed group signal A which is supplied to the current multiplexer 1 is supplied to the phase synchronizing part 51 via the selector part 55 as an original signal. In addition, the low-speed group signal A is subjected to a multiplexing in the current multiplexer 1 which outputs the high-speed group signal B. This high-speed group signal B is supplied to the high-speed group transmission path II and the demultiplexer 4 which functions as the reference part. The high-speed group signal B is demultiplexed in the demultiplexer 4 and is converted into a low-speed group signal C which is supplied to the phase synchronizing part 51 via the selector part 55.
The high-speed group signal B which is supplied to the current demultiplexer 2 is demultiplexed into the low-speed group signal A which is supplied to the phase synchronizing part 51 via the selector part 55. On the other hand, the high-speed group signal B is also supplied to the auxiliary demultiplexer 4 and is demultiplexed into the low-speed group signal C which is supplied to the phase synchronizing part 51 via the selector part 55.
The selector part 55 is controlled by a signal from the control part 53 and selectively supplies two signals to the phase synchronizing part 51. The two signals are the input signal of the current multiplexer 1 and the output signal of the auxiliary demultiplexer 4, the output signal of the current demultiplexer 2 and the output signal of the auxiliary demultiplexer 4, the input signal of the auxiliary multiplexer 3 and the signal from the test pattern generator part 54, or the output signal of the auxiliary demultiplexer 4 and the signal from the test pattern generator part 54.
Thereafter, the digital transmission terminal equipment operates as described above in conjunction with FIG. 1. The bit error detector part 52 detects the bit error based on the synchronized outputs of the phase synchronizing part 51 and outputs a detection signal. The control part 53 outputs an alarm signal based on the detection signal from the bit error detector part 52. The switches 6 and 7 are controlled responsive to the alarm signal which is output from the control part 53 of the bit comparison supervision part 5.
As shown in FIG. 3, a demultiplexer circuit 11 of the auxiliary demultiplexer 4 demultiplexes the high-speed group signal B into a low-speed group data DATA and a write clock signal WCLK. The write clock signal WCLK is multiplexed within the high-speed group signal B. In order to smoothen the output of the demultiplexer circuit 11 into the frequency of the original low-speed group signal A, the low-speed group data DATA is written into an elastic memory 12 in response to the write clock signal WCLK. A phase comparator 13 compares the phases of the write clock signal WCLK and a read clock signal RCLK which is generated by a phase locked loop (PLL) circuit 16. The PLL circuit 16 includes, in addition to the phase comparator 13, a lowpass filter 14 and a voltage controlled oscillator (VCO) 15 which feed back an output of the phase comparator 13 to the phase comparator 13. Although the illustration is omitted in FIG. 3, the circuit part including the elastic memory 12 and the PLL circuit 16 is provided for each low-speed group data DATA output from the demultiplexer circuit 11.
When making the bit comparison supervision of the stuff multiplexer having a redundancy system in the conventional digital transmission terminal equipment, there generally is a demand to reduce a time it takes for a main transmission circuit to be switched by the switches 6 and 7 to back up the line from a time when the device failure is detected. For this reason, a signal identical to the low-speed group signal A is generated by the test pattern generator part 54 of the bit comparison supervision part 5 and is supplied to the auxiliary multiplexer part 3. Hence, an automatic local scanning is periodically made by supplying the low-speed group signal C and the low-speed group signal A to the phase synchronizing part 51 via the auxiliary demultiplexer 4 which is used as the reference part and the selector part 55. As a result, the frequency with which the failure is detected in the auxiliary system (multiplexer and demultiplexer) and the current system (multiplexer and demultiplexer) is improved.
In the auxiliary demultiplexer 4 which is automatically testing the bit comparison supervision, the switching of the high-speed group signal takes place between a time when the local scan of the auxiliary and current multiplexer and demultiplexers and a time when a next local scan of the auxiliary and current multiplexer and demultiplexers starts. At an instant when the switching of the high-speed group signal takes place, the phase comparator 13 within the PLL circuit 16 of the auxiliary demultiplexer 4 receives no write clock signal WCLK, and as a result, the PLL circuit 16 enters a free-running state from a locked state.
After the PLL circuit 16 enters the free-running state, the PLL circuit 16 stabilizes at the frequency of the original low-speed group signal with a predetermined time constant which is peculiar to the PLL circuit 16. During the time in which the PLL circuit 16 stabilizes, there is a need to prohibit the bit comparison so as to prevent an erroneous detection of a bit error. Conventionally, a prohibiting time is timed by a kind of a timer within the control part 53 of the bit comparison supervision part 5, and the bit comparison is prohibited during the prohibiting time which corresponds to the time it takes for the PLL circuit 16 to stabilize.
According to the conventional method, the prohibiting time must be set independently for each PLL circuit 16 to match the time constant of each individual PLL circuit 16. In actual practice, however, it is virtually impossible to perfectly match the prohibiting time to the time constant of each PLL circuit 16. For this reason, the prohibiting time must be set with an added margin to ensure no erroneous detection of the bit error even for an estimated maximum time constant of the PLL circuit 16 used. As a result, the operation of detecting the bit error must be interrupted during the prohibiting time which is set in accordance with the estimated maximum time constant of the PLL circuit 16, and the bit error detection efficiency is poor. If the bit error detection frequency were increased by not adding the margin to the prohibiting time, an erroneous bit error detection would be made when the set prohibiting time is smaller than the time constant of the PLL circuit 16 used.
On the other hand, the high-speed group signal which is supplied to the demultiplexer circuit 11 of the auxiliary demultiplexer 4 is sequentially switched among the output of the current multiplexer 1, the input of the current demultiplexer 2 and the output of the auxiliary multiplexer 3. However, the three signals, that is, the output of the current multiplexer 1, the input of the current demultiplexer 2 and the output of the auxiliary multiplexer 3 are not synchronized to each other. As a result, the PLL circuit 16 enters the free-running state from the locked state every time the high-speed group signal supplied to the demultiplexer circuit 11 of the auxiliary demultiplexer 4 is switched. As described above, the prohibiting time must be set independently for each PLL circuit 16 to match the time constant of each individual PLL circuit 16, however, it is virtually impossible to perfectly match the prohibiting time to the time constant of each PLL circuit 16. For this reason, the prohibiting time must be set with the added margin to ensure no erroneous detection of the bit error even for the estimated maximum time constant of the PLL circuit 16 used.
Therefore, the conventional digital communication terminal equipment suffers from a problem in that it is impossible to simultaneously prevent the erroneous bit error detection while minimizing the prohibiting time to improve the bit error detection frequency.